The present invention relates to a package structure and a package process, and particularly relates to a stacked package structure and fabricating process thereof.
In today's information society, users all seek after electronic products with high speed, high quality and multiple functions. In terms of the product exterior appearance, electronic product designs reveal a trend of light weight, thinness and compactness. Therefore, various semiconductor device package techniques such as stacked semiconductor device package technique are proposed.
In the stacked semiconductor device package technique, several semiconductor devices are perpendicularly stacked together to form a package structure so that the package density is improved and the dimension of the package is decreased. Furthermore, by using three-dimensional stacking method to decrease the path length of the signal transmission between the semiconductor devices, rate of the signal transmission is improved and the semiconductor devices with different functions can be combined in the same package.
A conventional stacked semiconductor device package process is proposed by disposing a chip carrier on a circuit substrate first, and then a plurality of through silicon vias (TSV) are fabricated in the chip carrier after a molding process for electrically connecting a sequentially stacked upper chip with the circuit substrate.
To a conventional fabrication method, the through silicon vias are fabricated by grinding the chip carrier and the molding compound above the chip carrier until a top surface of each of the through silicon vias is exposed. Next, a selective etching process is performed to protruding an end of each of the through silicon vias from the chip carrier. However, the height of the chip carrier goes to be lower than that of the molding compound after the selective etching process is performed. For instance, the thickness of the chip carrier and the thickness of the molding compound being almost the same before the selective etching process goes different after the selective etching process, wherein a height difference between the chip carrier and the molding compound reaches 3˜5 μm or even goes beyond 5 μm. If so, the height of bumps on the upper chip may not satisfy the aforementioned height difference as bonding the upper chip to the chip carrier, such that a failure of electrical test occurs due to invalid bonding between the bumps and the through silicon vias, or the underfill can not be properly filled into a restricted space between the upper chip and the molding compound.